1. Field of the Invention
The present invention relates to a memory system including a memory and a controller controlling the memory and, in particular, to a technique for controlling a plurality of buffers of the memory which output data.
2. Description of the Prior Art
In a memory system, for reading out data stored at a certain address in a memory such as a DRAM (dynamic random access memory), a controller identifies the address by first designating a row address and then a column address. In response, the DRAM outputs the data stored at the identified address.
More specifically, the controller designates a row address to the DRAM by outputting it onto an address bus and then asserting a row address strobe signal line. Subsequently, the controller designates a column address to the DRAM by outputting it onto the address bus and then asserting a column address strobe signal line. When a target address is identified by asserting the column address strobe signal line, the DRAM outputs data stored in cells corresponding to the identified address via output buffers. For example, 32-bit data is outputted via 32 output buffers.
However, in the conventional memory system, the controller designates the column address at one time by asserting the column address strobe signal line. Accordingly, the DRAM outputs the 32-bit data stored at the address identified upon designation of the column address via the 32 output buffers at one time. This causes the current to flow through all the 32 output buffers simultaneously. In this event, a large amount of the current flows instantaneously so that a power supply voltage or a ground potential may fluctuate. This may render an operation of the DRAM unstable and cause an occurrence of EMI (electromagnetic interference).